In recent years, there has been known a semiconductor memory device which makes data storage nonvolatile by using a ferroelectric film as an insulating film for a capacitor. Transition of polarized state of a ferroelectric layer shows hysteresis characteristics, and remnant polarization exists in the ferroelectric layer even when a voltage applied to the ferroelectric layer becomes 0. Storage of nonvolatile data is performed utilizing the remnant polarization.
In order to read the nonvolatile data from the ferroelectric capacitor, it is necessary to apply a voltage to the ferroelectric capacitor, and generally, reading is carried out by driving a plate line that constitutes an electrode of the ferroelectric capacitor.
While the plate line usually drives plural memory cells that are arranged in a word line direction, the capacitance of the ferroelectric capacitor that is driven by the plate line is significantly larger than the capacitance of a capacitor that is made of a silicon oxide film and is usually adopted in a dynamic semiconductor memory device, and therefore, the load capacitance connected to the plate line becomes excessively large. Further, Ir or IrO is used as a constituent material of the plate line, and the resistances of these materials are high.
The excessive increase in the load capacitance connected to the plate line and the high resistance of the plate line lead to a problem that the access time of the memory device is significantly increased.
On the other hand, in order to drive the plate line at an appropriate speed, a MOS transistor of high driving ability must be used, leading to increased power consumption and enlarged layout area.
So, a circuit system and a circuit operation, such as a plate line voltage fixing system, have been proposed as a method for resolving the above-mentioned problems, i.e., the excessive increase in the load capacitance of the plate line and the increase in the layout area.
Hereinafter, a description will be given of a semiconductor memory equipped with a ferroelectric layer, as a first prior art that proposes a measure for solving the above-mentioned problems.
The first prior art discloses a semiconductor circuit that is operated in a state where a plate line is not driven and the voltage of the plate line is fixed, on the premise that the plate line driving system cannot avoid the above-mentioned problem (for example, refer to Japanese Published Patent Application No. Hei. 10-162587 (Patent Document 1)). According to this system, since the plate line is not driven, the plate line driving time is omitted to prevent an increase in access time.
By the way, it has conventionally been well known that the semiconductor memory device equipped with a ferroelectric layer has a problem that the ferroelectric capacitor characteristic is degraded by a reduction due to hydrogen which occurs during manufacturing processes.
So, as a method for preventing such degradation in the ferroelectric capacitor characteristic due to hydrogen, which is the problem of the first prior art, a technique of covering the periphery of the ferroelectric capacitor with a hydrogen barrier film has been proposed.
Hereinafter, a description will be given of a semiconductor memory device equipped with a ferroelectric layer according to second and third prior arts that propose a measure for solving the above-mentioned problem.
The second and third prior arts adopt a technique of enclosing a ferroelectric capacitor with a hydrogen barrier film, and disclose a construction in which electrical contact is made from beneath an upper electrode (for example, refer to Japanese Published Patent Application No. 2002-198494 (Patent Document 2), and Japanese Published Patent Application No. 2001-44376 (Patent Document 3)). According to this method, diffusion of hydrogen to the capacitor is prevented to prevent reduction of the capacitor due to hydrogen, thereby avoiding deterioration in the capacitor characteristic.
In the first to third prior arts, however, it is highly possible that the following drawbacks occur.
First of all, in the first prior art, a layout as shown in FIG. 4 is usually considered. Since the first prior art that is disclosed in the Patent Document 1 does not particularly specify a layout, FIG. 4 presumptively shows a generally considered layout.
FIG. 4 is a plan view of a semiconductor memory device 110 that is considered as a layout relating to the first prior art. In the semiconductor memory device, word lines WL extending in a column direction (DWL direction) are disposed, bit lines BL extending in a row direction (DBL direction) are disposed, a plate line CP as large as a memory cell array MA is disposed, sense amplifier circuits SA are adjacently disposed in the row direction (DBL direction) of the memory cell array MA, plate line voltage supply circuit CPD are adjacently disposed in the column direction (DWL direction) of the memory cell array MA, the bit lines BL are connected to the sense amplifier circuits SA, and the plate line CP is connected to the plate line voltage supply circuits CPD.
While this semiconductor memory device adopts an operation system with voltage of the plate line CP being fixed, usually supply of voltage to the plate line is performed at ends of the memory cell array MA.
However, the following problem has become evident by an analysis performed by the inventors. That is, in the case where supply of voltage to the plate line is performed at only the periphery of the memory cell array MA, since the resistance of the plate line is high in a nonoperating memory cell that is disposed in the vicinity of a specific memory cell that is operating, the voltage of the plate line is likely to occur temporal and local undershoot or overshoot, leading to degradation in data holding of the memory cell.
For example, when a memory cell at Pos1 shown in FIG. 4 is operated, the plate line voltage in the vicinity of the Pos1 varies.
At this time, although the plate line voltage in the vicinity of a nonoperating memory cell at Pos2 is supplied from the periphery of the memory cell array, insufficient voltage supply occurs because the resistance of the plate line is high, and thereby the plate line voltage in the vicinity of the Pos2 also varies with the variation in the plate line voltage in the vicinity of the Pos1.
As a result, an abbreviated writing operation of the memory cell in the vicinity of the Pos2 is undesirably carried out, leading to degradation in data holding of the memory cell.
Further, in order to solve this problem, the memory cell array MA may be constituted by plural small-scale memory cell arrays, and plural plate lines each having a size as large as each of the small-scale memory cells may be disposed for the respective memory cell arrays. In this case, however, it is necessary to provide plural plate line voltage generation circuit CPD, leading to an increase in the area of the semiconductor device.
Next, as for the second and third prior arts, layouts as shown in FIGS. 1 to 3 are usually considered. Since the second and third prior arts disclosed in the Patent Documents 2 and 3 do not particularly specify layouts, FIGS. 1 to 3 presumptively show generally considered layouts.
FIG. 1 is a plan view of a semiconductor memory device 210 that is conceivable as a first layout relating to the secondhand third prior arts. In the semiconductor memory device 210, plate lines CP and word lines WL, which extend in the column direction (DWL direction), are disposed, bit lines BL extending in the row direction (DBL direction) is disposed, and the memory cell MC is enclosed with a hydrogen barrier film.
FIG. 2 is a plan view of a semiconductor memory device 220 that is conceivable as a second layout relating to the second and third prior arts. In the semiconductor memory device 220, plate lines CP extending in the column direction (DWL direction) are connected to backing lines CPU for the plate lines CP in regions between plural hydrogen barrier films HB, where no hydrogen barrier films HB exist.
FIG. 3 is a cross-sectional view of the semiconductor memory device 220 that is conceivable as the second layout relating to the second and third prior arts, and it is taken along a line B1-B1′ in FIG. 2. The semiconductor memory device 220 has plate lines CP extending in the column direction (DWL direction), and each memory cell MC is enclosed with a hydrogen barrier film HB. The plate lines CP are connected to the backing lines CPU for the plate lines CP in regions between the plural hydrogen barrier films HB.
In this method, although the resistance of the plate lines CP reaches an unignorable level as miniaturization and high-integration of the semiconductor memory device are advanced, the backing lines CPU having a resistance lower than that of the plate lines CP are disposed above the hydrogen barrier film HB, and the lower plate lines CP and the upper backing lines CPU are connected, thereby to achieve speed-up.
However, in order to provide regions where the backing lines CPU and the plate lines CP are connected, it is necessary to provide regions where no hydrogen barrier film HB exists, leading to an increase in the area of the ferroelectric memory device.